The invention relates to a non-volatile memory device and, more particularly, to a non-volatile memory device having a charge trapping layer with improved erase characteristics and a method for fabricating the non-volatile memory device.
Semiconductor memory devices generally used for storing data are categorized as volatile or non-volatile memory devices. When the power supply is terminated, volatile memory devices lose stored data, but non-volatile memory devices maintain stored data. Accordingly, non-volatile memory devices are widely utilized in such devices as cellular phones, memory cards for storing music and/or image data, and other devices which are placed under adverse power conditions, e.g., discontinuous power supply, intermittent power breaks, or a need for low power consumption.
The cell transistor of such a non-volatile memory device has a stacked floating gate structure. The stacked floating gate structure includes a gate insulating layer, a floating gate electrode, an inter-gate insulating layer, and a control gate electrode sequentially stacked on a channel region of a cell transistor. However, the stacked floating gate structure has a limitation in improving an integration level of a memory device due to interference caused by the improvement in an integration level. Accordingly, there has been increased interest for a non-volatile memory device having a charge trapping layer.
A non-volatile memory device having a charge trapping layer includes a substrate having a channel region therein, a tunneling layer, a charge trapping layer, a blocking layer, and a control gate electrode stacked in this order. Such a structure is also called a “silicon-oxide-nitride-oxide-silicon (SONOS) structure” or a “metal-oxide-nitride-oxide-silicon (MONOS) structure.”
FIG. 1 is a cross-sectional view illustrating a non-volatile memory device having a general charge trapping layer. Referring to FIG. 1, a tunneling insulating layer 110 as a tunneling layer is arranged on a semiconductor substrate 100, e.g., a silicon substrate. A pair of impurity regions 102 (e.g., source/drain regions) are arranged in the semiconductor substrate 100. The impurity regions 102 are spaced apart from each other. A channel region 104 is arranged between the impurity regions 102. The tunneling insulating layer 110 is arranged on the channel region 104. A silicon nitride layer 120 as a charge trapping layer is arranged on the tunneling insulating layer 110. A blocking insulating layer 130 as a blocking layer is arranged on the silicon nitride layer 120. A control gate electrode 140 is arranged on the blocking insulating layer 130.
A process for operating the non-volatile memory device having such a structure is described in detail below. First, the control gate electrode 140 is positively charged and a predetermined bias voltage is applied to the impurity region 102. As a result, hot electrons are trapped from the substrate 100 into a trap site of the silicon nitride layer 120 as a charge trapping layer. Such a phenomenon is an operation for writing information in each memory cell or an operation for programming the memory cell. Similarly, the control gate electrode 140 is negatively charged and a predetermined bias voltage is applied to the impurity region 102. As a result, holes are trapped from the substrate 100 into the trap site of the silicon nitride layer 120 as a charge trapping layer. Then, the trapped holes are recombined with electrons present in the trap site. This phenomenon is an operation for erasing the programmed memory cell.
The non-volatile memory device having a general charge trapping layer has a disadvantage of low erase speed. More specifically, upon programming of the non-volatile memory device having this structure, electrons are trapped into a deep trap side, which is relatively far from the conduction band of the silicon nitride layer 120. For this reason, a relatively high voltage is needed to erase the device. In the case where a high voltage is applied to the control gate electrode 140 for erasing, there occurs backward tunneling in which electrons present in the control gate electrode 140 pass through the blocking insulating layer 130. For this reason, cells are undesirably programmed, and thus an error, e.g., an increase in threshold voltage occurs.
In order to prevent backward tunneling of electrons into the control gate electrode 140, it has been suggested to use in a non-volatile memory device a structure that uses high dielectric (high-k) materials such as aluminum oxide (Al2O3) for the blocking insulating layer 130, and to use sufficiently large work function metallic gates for the control gate electrode 140. Such a structure is also called a “metal-alumina-nitride-oxide-silicon (MANOS) structure.” This structure prevents backward tunneling, but fails to secure a desired erase speed due to the low trap density of the charge trapping layer, and it has a limitation in realizing a sufficiently low threshold voltage even after the erasing operation.